1. Field of the Invention
The present invention relates to a watchdog timer which monitors the operation of an electronic device, in particular, relates to such a device for the use of monitoring a one-chip micro-computer, and/or a one-chip micro-processor.
2. Background of the Invention
A watchdog timer is a sort of program timer which provides an alarm signal indicating a system error when a micro-computer program overruns.
The watchdog timer also has a counter which is reset every predetermined period while a computer-program operates correctly, and which overflows to output an alarm signal when is not reset after a predetermined period.
Said alarm signal is used for the initial reset of a hardware of a computer system, a trigger signal of an alarm buzzer, or an interruption signal for recovering from a software upset.
FIG.1A shows a block diagram of a prior-art watchdog timer acting as a program timer of which the initial preset value can be determined by a program.
The watchdog timer 1 has the register 2 for receiving preset data which determines a monitoring period the present data being preset by a writing signal W.sub.T in response to a preset instruction in a program, the counter 4 for counting the number of pulse .phi. which is provided every execution of an instruction of a computer, the comparator 3 for providing the coincidence output signal M when the content of the register 2 coincides with the content of the counter 4, and the start-stop control circuit 4' for controling the transmission of the clock pulse .phi. according to a start instruction and a stop instruction in a program.
The operation is described in accordance with FIG.1B.
When the writing signal W.sub.T (5") is applied to the watchdog timer 1, the initial data (DATA) is set in the register 2, while the counter 4 is reset to zero.
Then, when the start signal (START) is applied to the circuit 4' by the start instruction of a program, the counter 4 begins to be incremented by a clock pulse .phi..
When the next writing signal W.sub.T (5') is applied to the timer before the overflow of the counter 4, the next data is restored in the register 2 to restart the counting operation by the counter 4, without generating the coincidence signal M of a high level from the comparator 4.
The preset value of the register 2 can be readily changed by the data (DATA) to change a period of time of the writing signal W.sub.T.
On the other hand, when there is something wrong with the operation of the program, the writing signal W.sub.T (6) is not normally provided, but the writing signal (8) is applied at a delayed timing, therefore the counter 4 overflows. In this case, the comparator 3 provides the coincidence signal M of a "high" level which indicates computer upset.
However, the watchdog timer of FIG. 1A has the disadvantage that it cannot detect such a program error as a writing signal appears early to a normal pulse to be generated at a predetermined preset time, although it can detect such a program error as a writing signal appears lately to a normal pulse to be generated at a predetermined preset time.
Accordingly, a prior art watchdog timer is not enough for detecting all possible errors of a program, therefore a more reliable watchdog timer has been desired.